<?xml version="1.0" encoding="utf-8" ?> <rss version="2.0" xmlns:opensearch="http://a9.com/-/spec/opensearch/1.1/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:atom="http://www.w3.org/2005/Atom"> <channel> <title> <![CDATA[MKSSS's Union Search for 'au:&quot;Bhaskar J.&quot;']]> </title> <!-- prettier-ignore-start --> <link> http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-search.pl?idx=&#38;q=au%3A%22Bhaskar%20J.%22&#38;sort_by=relevance&#38;format=rss </link> <!-- prettier-ignore-end --> <atom:link rel="self" type="application/rss+xml" href="http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-search.pl?idx=&#38;q=au%3A%22Bhaskar%20J.%22&#38;sort_by=relevance&#38;format=rss" /> <description> <![CDATA[ Search results for 'au:&quot;Bhaskar J.&quot;' at MKSSS's Union]]> </description> <opensearch:totalResults>15</opensearch:totalResults> <opensearch:startIndex>0</opensearch:startIndex> <opensearch:itemsPerPage>50</opensearch:itemsPerPage> <atom:link rel="search" type="application/opensearchdescription+xml" href="http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-search.pl?idx=&#38;q=au%3A%22Bhaskar%20J.%22&#38;sort_by=relevance&#38;format=opensearchdescription" /> <opensearch:Query role="request" searchTerms="idx%3D%26q%3Dau%253A%2522Bhaskar%2520J.%2522" startPage="" /> <item> <title> VHDL Synthesis Primer </title> <dc:identifier>ISBN:</dc:identifier> <!-- prettier-ignore-start --> <link>http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-detail.pl?biblionumber=303084</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <p> By Bhaskar J..<br /> BS Publication 2001 .<br /> 296 </p> ]]> <![CDATA[ <p> <a href="http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-reserve.pl?biblionumber=303084">Place hold on <em>VHDL Synthesis Primer</em></a> </p> ]]> </description> <guid>http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-detail.pl?biblionumber=303084</guid> </item> <item> <title> Static Timing Analysis For Nanometer Designs A Practical Approach </title> <dc:identifier>ISBN:9781441947154</dc:identifier> <!-- prettier-ignore-start --> <link>http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-detail.pl?biblionumber=369793</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/1441947159.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Bhaskar J ..<br /> Springer 9781441947154 </p> ]]> <![CDATA[ <p> <a href="http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-reserve.pl?biblionumber=369793">Place hold on <em>Static Timing Analysis For Nanometer Designs A Practical Approach</em></a> </p> ]]> </description> <guid>http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-detail.pl?biblionumber=369793</guid> </item> <item> <title> Verilog HDL Synthesis A Practical Primer </title> <dc:identifier>ISBN:</dc:identifier> <!-- prettier-ignore-start --> <link>http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-detail.pl?biblionumber=303083</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <p> By Bhaskar J..<br /> BS Publication 2001 .<br /> 294 </p> ]]> <![CDATA[ <p> <a href="http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-reserve.pl?biblionumber=303083">Place hold on <em>Verilog HDL Synthesis </em></a> </p> ]]> </description> <guid>http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-detail.pl?biblionumber=303083</guid> </item> <item> <title> VHDL Synthesis Primer </title> <dc:identifier>ISBN:</dc:identifier> <!-- prettier-ignore-start --> <link>http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-detail.pl?biblionumber=302509</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <p> By Bhaskar J..<br /> BS Publication 2001 .<br /> 296 </p> ]]> <![CDATA[ <p> <a href="http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-reserve.pl?biblionumber=302509">Place hold on <em>VHDL Synthesis Primer</em></a> </p> ]]> </description> <guid>http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-detail.pl?biblionumber=302509</guid> </item> <item> <title> Verilog HDL Synthesis A Practical Primer </title> <dc:identifier>ISBN:</dc:identifier> <!-- prettier-ignore-start --> <link>http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-detail.pl?biblionumber=301874</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <p> By Bhaskar J..<br /> BS Publication 2001 .<br /> 215 </p> ]]> <![CDATA[ <p> <a href="http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-reserve.pl?biblionumber=301874">Place hold on <em>Verilog HDL Synthesis </em></a> </p> ]]> </description> <guid>http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-detail.pl?biblionumber=301874</guid> </item> <item> <title> VHDL Primer </title> <dc:identifier>ISBN:9788120323667</dc:identifier> <!-- prettier-ignore-start --> <link>http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-detail.pl?biblionumber=52435</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/8120323661.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Bhaskar, J..<br /> Delhi PHI Learing Pvt. Ltd. 2014 .<br /> XX; 373P. 9788120323667 </p> ]]> <![CDATA[ <p> <a href="http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-reserve.pl?biblionumber=52435">Place hold on <em>VHDL Primer</em></a> </p> ]]> </description> <guid>http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-detail.pl?biblionumber=52435</guid> </item> <item> <title> VHDL Primer </title> <dc:identifier>ISBN:0-13-242843-1</dc:identifier> <!-- prettier-ignore-start --> <link>http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-detail.pl?biblionumber=300387</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0132428431.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Bhaskar J..<br /> Awp 2000 .<br /> 372 0-13-242843-1 </p> ]]> <![CDATA[ <p> <a href="http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-reserve.pl?biblionumber=300387">Place hold on <em>VHDL Primer</em></a> </p> ]]> </description> <guid>http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-detail.pl?biblionumber=300387</guid> </item> <item> <title> A VHDL Synthesis Primer </title> <dc:identifier>ISBN:9788178000145</dc:identifier> <!-- prettier-ignore-start --> <link>http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-detail.pl?biblionumber=52467</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/8178000148.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Bhaskar, J..<br /> Hyderabad B.S. Publication 2013 .<br /> XVII; 296P. 9788178000145 </p> ]]> <![CDATA[ <p> <a href="http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-reserve.pl?biblionumber=52467">Place hold on <em>A VHDL Synthesis Primer</em></a> </p> ]]> </description> <guid>http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-detail.pl?biblionumber=52467</guid> </item> <item> <title> VHDL Synthesis Primer </title> <dc:identifier>ISBN:</dc:identifier> <!-- prettier-ignore-start --> <link>http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-detail.pl?biblionumber=303092</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <p> By Bhaskar J..<br /> BS Publication 2001 .<br /> 296 </p> ]]> <![CDATA[ <p> <a href="http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-reserve.pl?biblionumber=303092">Place hold on <em>VHDL Synthesis Primer</em></a> </p> ]]> </description> <guid>http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-detail.pl?biblionumber=303092</guid> </item> <item> <title> Verilog HDL Synthesis A Practical Primer </title> <dc:identifier>ISBN:</dc:identifier> <!-- prettier-ignore-start --> <link>http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-detail.pl?biblionumber=302510</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <p> By Bhaskar J..<br /> BS Publication 2001 .<br /> 296 </p> ]]> <![CDATA[ <p> <a href="http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-reserve.pl?biblionumber=302510">Place hold on <em>Verilog HDL Synthesis </em></a> </p> ]]> </description> <guid>http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-detail.pl?biblionumber=302510</guid> </item> <item> <title> VHDL Primer </title> <dc:identifier>ISBN:0-13-242843-1</dc:identifier> <!-- prettier-ignore-start --> <link>http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-detail.pl?biblionumber=300562</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0132428431.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Bhaskar J..<br /> Addison Weseley 2000 .<br /> 374 0-13-242843-1 </p> ]]> <![CDATA[ <p> <a href="http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-reserve.pl?biblionumber=300562">Place hold on <em>VHDL Primer</em></a> </p> ]]> </description> <guid>http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-detail.pl?biblionumber=300562</guid> </item> <item> <title> VHDL Synthesis Primer </title> <dc:identifier>ISBN:</dc:identifier> <!-- prettier-ignore-start --> <link>http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-detail.pl?biblionumber=303091</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <p> By Bhaskar J..<br /> BS Publication 2001 .<br /> 296 </p> ]]> <![CDATA[ <p> <a href="http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-reserve.pl?biblionumber=303091">Place hold on <em>VHDL Synthesis Primer</em></a> </p> ]]> </description> <guid>http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-detail.pl?biblionumber=303091</guid> </item> <item> <title> Verilog HDL Synthesis A Practical Primer </title> <dc:identifier>ISBN:</dc:identifier> <!-- prettier-ignore-start --> <link>http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-detail.pl?biblionumber=303088</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <p> By Bhaskar J..<br /> BS Publication 2001 .<br /> 215 </p> ]]> <![CDATA[ <p> <a href="http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-reserve.pl?biblionumber=303088">Place hold on <em>Verilog HDL Synthesis </em></a> </p> ]]> </description> <guid>http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-detail.pl?biblionumber=303088</guid> </item> <item> <title> Verilog HDL Synthesis A Practical Primer </title> <dc:identifier>ISBN:</dc:identifier> <!-- prettier-ignore-start --> <link>http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-detail.pl?biblionumber=303087</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <p> By Bhaskar J..<br /> BS Publication 2001 .<br /> 215 </p> ]]> <![CDATA[ <p> <a href="http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-reserve.pl?biblionumber=303087">Place hold on <em>Verilog HDL Synthesis </em></a> </p> ]]> </description> <guid>http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-detail.pl?biblionumber=303087</guid> </item> <item> <title> VHDL Primer </title> <dc:identifier>ISBN:978-91-203-2366-7</dc:identifier> <!-- prettier-ignore-start --> <link>http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-detail.pl?biblionumber=50782</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <p> By Bhaskar J.<br /> New Delhi PHI Publlication 2013 .<br /> XX;373 P 978-91-203-2366-7 </p> ]]> <![CDATA[ <p> <a href="http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-reserve.pl?biblionumber=50782">Place hold on <em>VHDL Primer</em></a> </p> ]]> </description> <guid>http://mksss.mapmyelibrary.com:8083/cgi-bin/koha/opac-detail.pl?biblionumber=50782</guid> </item> </channel> </rss>
