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|---|---|---|---|
| 008 | 230718s9999 xx 000 0 und d | ||
| 041 | _aeng | ||
| 082 |
_a621.39'2 _bPAL |
||
| 100 | _aPalnitkar S. | ||
| 245 |
_aVerilog HDL _bA Guide To Digital Design And Synthesis |
||
| 260 |
_c2002 _bPearson |
||
| 300 | _a397 | ||
| 365 |
_cRs. _b336.01 |
||
| 700 | _aPalnitkar S. | ||
| 906 |
_dB:80701-Oct-2002 _cETC _b53.7616 |
||
| 999 |
_c304427 _d304427 |
||