| 000 | 00509nam a2200181Ia 4500 | ||
|---|---|---|---|
| 008 | 230718s9999 xx 000 0 und d | ||
| 020 | _a9788177589184 | ||
| 041 | _aeng | ||
| 082 |
_a621.39'2 _bPAL |
||
| 100 | _aPalnitkar S. | ||
| 245 |
_aVerilog HDL _bA Guide To Digital Design And Synthesis,IEEE 1364-2001 Compliant |
||
| 250 | _a2nd ed. | ||
| 260 |
_c2003 _bPearson |
||
| 300 | _a490 | ||
| 365 |
_cRs. _b640.00 |
||
| 700 | _aPalnitkar S. | ||
| 906 |
_dO:0669709-Oct-2019B:963401-Oct-2019 _cBETC _b1600 |
||
| 999 |
_c350521 _d350521 |
||